Inscrit le: 09 Mai 2018
|Posté le: Mer 23 Mai - 07:00 (2018) Sujet du message: Why does Oh! Library AXI convert between eMesh and Packets
So first off. I am an FPGA noob. I have not touched HDL (and we used VHDL) since college. I wanted a project board and was having trouble deciding between an FPGA development board and something for embedded software development. But my other passion is massive parallelism. So when I saw the Parallella board on Amazon, I was so excited. 16-cores + 2 ARM for me to see how much extra throughput I can get from my algorithms using different synchronization constructs, or lock-free approaches, awesome! But at the same time I really regretted not learning more about hardware development, since I get very interested when I hear about stories like Microsoft using FPGAs to accelerate network cards on their hypervisors in the Azure cloud.
Ok enough with the digression. So I'm trying to understand the accelerator demo. I want to do something similar. See if I can implement an AXI slave that accelerates something like SHA256 hashing. What I cannot seem to understand is why the simple accelerator has instantiations (is that the correct term?) of modules that do conversion from eMesh to "packet" and vice versa? Once again, I've just been perusing the HDL and source, and I could be way off. Is it because the DMA controller is also implemented by Adapteva, and is it because the memory management module requires the the messages to be in "eMesh" format to determine if they get routed to DRAM or the Epiphany co-processor? If so then what exactly does AXI provide when you've layered your own protocol on top of it?
I didn't find the right solution from the internet.
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